jetson-customize-pcie

Customize PCIe (per-controller status / lanes / speed) Overview PCIe on Tegra264 (Thor, pcie@C0..C5 ) and Tegra234 (Orin, pcie@C0..C10 ) is split across multiple controllers that share the UPHY lane pool with USB3 / MGBE / UFS. Each controller's runtime behavior is determined by two surfaces, both required : Surface Target Authoritative for ODMDATA pcie@N_status=… (+ pcie@N_max-link-speed , pcie@N_pcie-mode , pcie@N_clk-scheme , pcie-cN-endpoint-enable ) /pcie/pcie@N in BPMP DTB UPHY lane power, refclk gating, controller-side power rails Kernel-DT overlay on &pcieN /bus@0/pcie@ in kernel DTB Kernel probe, lane width, link speed, RC/EP mode Skipping the kernel overlay on a disable lets the kernel probe a powered-down PHY (link timeouts in dmesg). Skipping the ODMDATA token on a disable leaves BPMP holding the PHY hot. Show more Installs 706 Repository nvidia/skills GitHub Stars 2.4K First Seen Jun 22, 2026 Security Audits Gen Agent Trust Hub Pass Socket Pass Snyk Pass